We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP's are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
All our verification components comes with advanced command, configuration and status reporting interface. This is very simple to use and debug. We use lot of automation for writing Verification IP, so time to develop any verification IP is very efficient and faster. If you need any verification IP which is not listed below, please do let us know. We can develop it very fast for you.