Verification IP's

We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP's are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

All our verification components comes with advanced command, configuration and status reporting interface. This is very simple to use and debug. We use lot of automation for writing Verification IP, so time to develop any verification IP is very efficient and faster. If you need any verification IP which is not listed below, please do let us know. We can develop it very fast for you.

We have more than 60 customers using our Verification IP's. Most of the top semiconductor companies are our customers

 

 

Visit us at Booth 411 at DAC 2014

 

 

MIPI Verification IP's

Networking and SOC Verification IP's

Automotive And Serial Bus Verification IP's

Storage And Misc Verification IP's

Memory Models

     

Design IP's

We develop Design Components, leveraging our rich experience in ASIC / SoC design and capabilities on Verilog and VHDL. Our Design components are configurable, reusable plug-and-play design solutions for standard interfaces based on Verilog and VHDL. All our design components comes with advanced configuration and status reporting interface. All our Design components are validated using our Verification IP's which has been used to tapeout multiple ASIC by our customers, Also each of design IP is tested on FPGA platform. We use lot of automation for writing Design IP, so time to develop any design IP is very efficient and faster. If you need any design IP which is not listed below, please do let us know. We can develop it very fast for you.

Note : Our design IP are proven in FPGA.

 

Design IP's

  • UART : Available
  • SMBus Slave : Under Development
  • SMBus Master: Under Development
  • SGMII MAC : Available
  • GMII MAC : Available
  • XGMII MAC : Available
  • MDIO Master/Slave : Available
  • SPI Master : Available
  • I2C/SPI Slave : Available
  • PMBus Slave : Under Development
  • PMBus master: Under Development


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