BVCI Verification IP provides an smart way to verify the BVCI component of a SOC or a ASIC. The SmartDV's BVCI Verification IP is fully compliant with standard BVCI Specification and provides the following features.
BVCI VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Compliant to BVCI Protocol version 2.0
Support for all types of AMBA APB devices
Master
Slave
Support for programmable wait states, Split completion
Supports generation of out of order transcations
Configurable transfer size for read and write transactions
Flexibility to send completely configured data
Ability to inject errors during data transfer
On-the-fly protocol and data checking
Benefits
Faster testbench development and more complete verification of BVCI designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
