BVCI Verification IP provides an smart way to verify the BVCI component of a SOC or a ASIC. The SmartDV's BVCI Verification IP is fully compliant with standard BVCI Specification and provides the following features.
BVCI VIP is supported natively in Verilog and VHDL
- Compliant to BVCI Protocol version 2.0
- Support for all types of AMBA APB devices
- Support for programmable wait states, Split completion
- Supports generation of out of order transcations
- Configurable transfer size for read and write transactions
- Flexibility to send completely configured data
- Ability to inject errors during data transfer
- On-the-fly protocol and data checking
- Faster testbench development and more complete verification of BVCI designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- BVCI Verification Env
SmartDV's BVCI Verification env contains following.
- Complete regression suite containing all the BVCI testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.