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About Us
SmartDV was started in August 2007 by groups of engineers. Together these engineers have more than 30 years experience in design and verification of complex ASIC's. The staff consultants are among the best and brightest minds in the industry. We maintain our leadership by continuously staying atop the latest technology advances and bringing that information to our clients. Our biggest strength is ablity to automate writing of verification enviroment and testcases for ASIC verification to save huge time it takes to verify ASIC's
SmartDV offers design and verification services in the area of ASIC and FPGA design, with emphasis on quality deliverables. Our offerings are designed to function with minimal customer involvement, and the process ensures flawless and timely delivery be it designs starting from specifications or point services. SmartDV offers industry standard Verification IP like I2C, ethernet, lin, Flexray, SATA, SAS, SPI, Fiber Channel, OCP in SystemVerilog. We can offer VIP's in any lanaguage (OpenVera, E, SystemC)
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