OpenCores Wishbone B3 Verification IP provides an smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC. The SmartDV's OpenCores Wishbone B3 Verification IP is fully compliant with standard OpenCores Wishbone B3 Specification and provides the following features.
OpenCores Wishbone B3 VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Compliant to OpenCores Wishbone B3 Protocol
Support for all types of Wishbone Wishbone devices
Master
Slave
Support for programmable wait states
Support for programmable Retry insertion
Support for programmable Error insertion
Configurable transfer size for read and write transactions
Support for linear,Fixed and Wrap burst sizes.
Flexibility to send completely configured data
Ability to inject errors during data transfer
On-the-fly protocol and data checking
Benefits
Faster testbench development and more complete verification of OpenCores Wishbone B3 designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
