PVCI VIP

PVCI Verification IP provides an smart way to verify the PVCI component of a SOC or a ASIC. The SmartDV's PVCI Verification IP is fully compliant with standard PVCI Specification and provides the following features.

PVCI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

 

Features

  • Compliant to PVCI Protocol version 2.0
  • Support PVCI Master, PVCI Slave, PVCI Monitor and PVCI Checker.
  • Supports all PVCI data and address widths.
  • Supports 8-bit, 16-bit and 32-bit devices.
  • Simple packet and burst transfer support.
  • Supports constrained randomization of protocol attributes.
  • Slave supports fine grain control of response per address or per transfer.
  • Programmable Wait state insertion.
  • Configurable PVCI interface size for read and write transfers.
  • Ability to inject errors during data transfer.
  • Flexibility to send completely configured data
  • Supports FIFO memory.
  • Rich set of configuration parameters to control PVCI functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in master, slave and monitor for various events.
  • Status counters for various events on bus.
  • PVCI Verification IP comes with complete testsuite to test every feature of PVCI specification.

Benefits

  • Faster testbench development and more complete verification of PVCI designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
 

PVCI Verification Env

SmartDV's PVCI Verification env contains following.

  • Complete source code of PVCI Monitor and BFM.
  • Complete regression suite containing all the PVCI testcases.
  • Examples's showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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