PVCI Verification IP provides an smart way to verify the PVCI component of a SOC or a ASIC. The SmartDV's PVCI Verification IP is fully compliant with standard PVCI Specification and provides the following features.
PVCI VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Compliant to PVCI Protocol version 2.0
Support for all types of AMBA APB devices
Master
Slave
Support for programmable wait states
Configurable transfer size for read and write transactions
Supports insertion and detection of all types of errors
Flexibility to send completely configured data
Ability to inject errors during data transfer
On-the-fly protocol and data checking
Benefits
Faster testbench development and more complete verification of PVCI designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
