UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The SmartDV's UART Verification IP is fully compliant with standard UART 16550 Specification and provides the following features.

UART VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env



  • Fully compatible with 16550
  • Transmit and receive commands allow the user to transmit and receive UART data
  • Support additional functionality of IRDA, RS232 and GPIO.
  • Full duplex operation
  • Fully configurable serial interface
  • Configurable receive FIFO depth
  • Configurable baud rate
  • Programmable hardware flow control
  • Supports different types of parity insertion
    • Even parity
    • Odd parity
    • Space parity
    • Mark parity
    • No parity
  • Supports number of stop bit configuration
  • Supports character width of 5,6,7, and 8 bits
  • Supports 16 General purpose output and input pins
  • Error injection capability
    • Parity error
    • Framing error
  • Supports constraints Randomization.
  • Callbacks in transmitter, receiver and monitor for user processing of data.
  • Functional coverage for complete 16550 features.
  • On-the-fly protocol and data checking


  • Faster testbench development and more complete verification of UART designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

UART Verification Env

SmartDV's UART Verification env contains following.

  • Complete regression suite containing all the UART testcases.
  • Examples's showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

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