UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The SmartDV's UART Verification IP is fully compliant with standard UART 16550 Specification and provides the following features.
UART VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Fully compatible with 16550
Transmit and receive commands allow the user to transmit and receive UART data
Full duplex operation
Fully configurable serial interface
Configurable receive FIFO depth
Configurable baud rate
Programmable hardware flow control
Supports different types of parity insertion
Supports number of stop bit configuration
Supports Character width of 5,6,7, and 8 bits
Supports 16 General purpose output and input pins
Error injection capability
On-the-fly protocol and data checking
Benefits
Faster testbench development and more complete verification of UART designs.
Easy to use command interface simplifies testbench control and configuration of TX and RX.
