AVCI VIP

AVCI Verification IP provides an smart way to verify the AVCI component of a SOC or a ASIC. The SmartDV's AVCI Verification IP is fully compliant with standard AVCI Specification and provides the following features.

AVCI VIP is supported for VMM, RVM, AVM, OVM and non-standard verification env

 

Features

  • Compliant to AVCI Protocol version 2.0
  • Support for all types of AMBA APB devices
    • Master
    • Slave
  • Support for programmable wait states, Split completion
  • Supports generation of out of order transcations
  • Configurable transfer size for read and write transactions
  • Flexibility to send completely configured data
  • Ability to inject errors during data transfer
  • On-the-fly protocol and data checking
  • Benefits

  • Faster testbench development and more complete verification of AVCI designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
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    AVCI Verification Env

    SmartDV's AVCI Verification env contains following.

    • Complete SystemVerilog source code of AVCI Monitor and BFM.
    • Complete regression suite containing all the AVCI testcases.
    • Examples's showing how to connect various components, and usage of BFM and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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