MIPI HSI VIP

MIPI HSI VIP

MIPI HSI Verification IP provides an smart way to verify the MIPI HSI uni-directional two-wire bus. The SmartDV's MIPI HSI Verification IP is fully compliant with version 1.01 MIPI Alliance specification for serial Interface and provides the following features.

MIPI HSI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Supports 1.01 MIPI HSI Specification.
• Full MIPI HSI Tx and Rx functionality.
• Monitor,Detects and notifies the testbench of all protocol and timing errors.
• Supports data flow
• Synchronized data
• Pipelined data
• Receiver real time data
• Supports both type of transmission modes on transmit interface
• Stream transmission mode
• Frame transmission mode
• Supports wake signal functionality
• Error injection capabilities on transmitter interface
• Missed clock cycles
• Additional clock cycles
• Signal error
• Invalid command frame error
• Invalid message sequence error
• Invalid channel error
• Reserved bit error
• Invalid response frame error
• Run-Time configurability for transmitters
• Data Rate change
• Run-Time configurability for receivers
• Data Rate change
• Time out counter ON/OFF
• Time out counter
• Tailing bit counter ON/OFF
• Tailing bit counter
• Frame burst counter ON/OFF
• Frame burst counter
• Supports protocol
• Data link protocol
• Audio protocol
• Programmable number of channels for data transfer.
• Programmable PDU length from 0 to 256 kb.
• Supports Speech data frame and audio data frame
• Resynchronization supported for data link protocol
• Status counters for various events in bus.
• Callbacks in node transmitter, receiver and monitor for user processing of data.
• MIPI HSI Verification IP comes with complete test suite to test every feature of MIPI HSI specification.
• Functional coverage for complete MIPI HSI features

Benefits

• Faster testbench development and more complete verification of MIPI HSI designs.
• Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
• Simplifies results analysis.
• Runs in every major simulation environment.

MIPI HSI Verification Env

SmartDV's MIPI HSI Verification env contains following.

• Complete source code of MIPI HSI Monitor,Rx,Tx.
• Complete regression suite containing all the MIPI HSI testcases.
• Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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