MII/GMII/RGMII/SGMII Ethernet VIP

The 10/100/1Gigabit Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1000M Ethernet interface MII/GMII/RGMII/SGMII. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.

MII/GMII/RGMII/SGMII Ethernet VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

 

Features

  • Follows MII/GMII specification as defined in IEEE 802.3
  • Follows RGMII specification 2.0
  • Follows SGMII specification 1.8
  • Supports all types of MII/GMII TX and RX errors insertion/detection
  • Comes with MII/GMII/RGMII/SGMII Tx BFM, MII/GMII/RGMII/SGMII Rx BFM, and MII/GMII/RGMII/SGMII Monitor
  • Monitor supports detection of all protocol violations
  • Supports Pause frame generation and detection
  • Built in coverage analysis
  • Callbacks in master and slave for various events
  • Status counters for various events in bus
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    Benefits

  • Faster testbench development and more complete verification of MII/GMII/RGMII/SGMII designs
  • Easy to use command interface simplifies testbench control and configuration of MII/GMII/RGMII/SGMII TX and RX
  • Simplifies results analysis
  • Runs in every major simulation environment
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    MII/GMII Verification Env

    SmartDV's MII/GMII/RGMII/SGMII Verification env contains following.

    • Complete SystemVerilog source code of MII/GMII/RGMII/SGMII Monitor, TX and RX BFM.
    • Complete regression suite (UNH) containing all the MII/GMII testcases.
    • Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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