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Products

DDR5 IIP

DDR5 IIP

DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 Rev095 specification and DFI-version 5.0 Compliant. Through its DDR5 compatibility,it provides a simple interface to a wide range of low-cost devices. DDR5 IIP is proven in FPGA environment.The host interface of the DDR5 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

DDR5 IIP is supported natively in Verilog and VHDL

Features
  • Supports DDR5 protocol standard JESD79-5 Rev095 Specification.
  • Compliant with DFI version 5.0 Specification.
  • Supports up to 64GB device density.
  • Supports the following device types:
    • X4
    • X8
    • X16
  • Supports all speed grades as per specification.
  • Supports for Mode Registers programming.
  • Supports for Sequential burst type.
  • Supports Programmable burst lengths of 8,16 and 32.
  • Supports for Programmable Write and Read latency.
  • Supports Multiple Outstanding transaction.
  • Supports In-port Arbitration using QoS.
  • Supports for Write Data Mask.
  • Supports for Data Bus Inversion (DBI) for write and read.
  • Supports CRC and ECC for Write and Read Operations.
  • Supports for Self Refresh and Power Down operation.
  • Supports for Precharge Command modes.
  • Supports for Maximum Power Saving Mode (MPSM).
  • Supports 1:4 Controller to DFI PHY frequency ratio.
  • Supports Programmable clock frequency operation.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices.
Benefits
  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    Request Datasheet
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    SmartDV's DDR5 IP contains following

  • The DDR5 interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

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