PMBus VIP

PMBus VIP

PMBus Verification IP provides an smart way to verify the PMBus component of a SOC or a ASIC. The SmartDV's PMBus Verification IP is fully compliant with standard PMBus 1.2 Specification and provides the following features.

PMBus VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Fully compatible with PMBus 1.2 Specification
• Operates as a Master, Slave, or both.
• Support alert operation
• Support following commands
• Send byte command
• Receive byte command
• Write byte command
• Write word command
• Read byte command
• Read word command
• Process call command
• Block write command
• Block read command
• Group command
• Block write and read process call command
• Extended command read byte
• Extended command read word
• Extended command write byte
• Extended command write word
• Page Plus write command
• Page Plus read command
• Supports following types of error injection and detection
• NACK for read data from master for bytes which is not last byte
• NACK for write data from slave for write data
• Master acked last read data
• Master is driving SCL after sending NACK for read data
• Master aborted in middle of byte transfer
• Packet error check error
• NACK for PEC code by slave
• ACK for PEC code by master
• Master asserted stop condition before PEC byte
• NACK for Command code byte by slave
• NACK for second address byte after repeated start to same slave
• NACK for write size byte
• NACK for read size byte
• More than expected bytes were send or received
• Less than expected bytes were send or received
• Number of bytes field and actual bytes don't match
• Implements all the registers and commands as per the PMBus specification
• Monitor, Detects and notifies the testbench of all protocol and timing errors.
• Compares read data with expected results
• Bus-accurate timing
• Various kind of Master and Slave errors generation
• Glitch monitor and injection.
• Callbacks in master and slave for various events.
• Status counters for various events in bus.

Benefits

• Faster testbench development and more complete verification of PMBus designs.
• Easy to use command interface simplifies testbench control and configuration of master and slave
• Simplifies results analysis.
• Runs in every major simulation environment.

PMBus Verification Env

SmartDV's PMBus Verification env contains following.

• Complete source code of PMBus Monitor and BFM.
• Complete regression suite containing all the PMBus testcases.
• Examples's showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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