PMBus VIP

PMBus Verification IP provides an smart way to verify the PMBus component of a SOC or a ASIC. The SmartDV's PMBus Verification IP is fully compliant with standard PMBus 1.1 Specification and provides the following features.

PMBus VIP is supported for VMM, RVM, AVM, OVM and non-standard verification env

 

Features

  • Fully compatible with PMBus 1.1 Specification
  • Operates as a Master, Slave, or both.
  • Monitor, Detects and notifies the testbench of all protocol and timing errors.
  • Compares read data with expected results
  • Bus-accurate timing
  • Various kind of Master and Slave errors generation
  • Glitch monitor and injection.
  • Callbacks in master and slave for various events.
  • Status counters for various events in bus.
  • Benefits

  • Faster testbench development and more complete verification of PMBus designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
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    PMBus Verification Env

    SmartDV's PMBus Verification env contains following.

    • Complete SystemVerilog source code of PMBus Monitor and BFM.
    • Complete regression suite containing all the PMBus testcases.
    • Examples's showing how to connect various components, and usage of BFM and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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