SmartDV Fiber Channel Verification IP

Fiber Channel

Fiber Channerl Verification IP provides an smart way to verify the Fiber channel MAC, PCS and serdes of a SOC or a ASIC. The SmartDV's Fiber Channel verification IP is fully compliant with standard Fiber channel Specification and provides the following features.

Fiber Channel is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

Features

Supports generation all types of FC frames

Supports verification of all layers of fiber channel.

Supports injection of errors at each layer

Comes with complete testsuite to do compliance testing of fiber channel

Functional coverage of all the frame fields and errors injected

Supports Callbacks, so that user can access the data observed by monitor

Benefits

Faster testbench development and more complete verification of Fiber Channel designs.

Easy to use command interface simplifies monitor control and configuration.

Simplifies results analysis.

Runs in every major simulation environment.

Fiber Channel Verification Env

SmartDV's Fiber Channel Verification env contains following.

Complete SystemVerilog source code of Fiber Channel.
Examples's showing how to connect and usage of Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.