Fiber Channel

Fiber Channerl Verification IP provides an smart way to verify the Fiber channel MAC, PCS and serdes of a SOC or a ASIC. The SmartDV's Fiber Channel verification IP is fully compliant with standard Fiber channel Specification and provides the following features.

Fiber Channel is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env



  • Supports generation all types of FC frames
  • Supports verification of all layers of fiber channel.
  • Support following interfaces
    • 10 or 20 bit Phy interfaces
    • 8 bit Encoder / Decoder interface
    • 32 bit Dword Primitive interface
    • Dword level transport interface
    • Complete Frame transaction level interface
  • Supports injection of errors at each layer
    • Invalid frame fields
    • Invalid eof and sof injection
    • Oversize and undersize frames
    • disparity errors
    • Invalid code group errors
    • Invalid K and D character injection
    • CRC error injection
    • Retry control
  • Support Port Login and Process Login
  • A single Initiator can communicate with multiple Targets.
  • Supports multi LUN addressing
  • Supports speeds up to 16G
  • Comes with complete testsuite to do compliance testing of fiber channel
  • Functional coverage of all the frame fields and errors injected
  • Supports Callbacks, so that user can access the data observed by monitor


  • Faster testbench development and more complete verification of Fiber Channel designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Fiber Channel Verification Env

SmartDV's Fiber Channel Verification env contains following.

  • Examples's showing how to connect and usage of Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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