MIPI DPI Verification IP provides an smart way to verify the MIPI DPI bus. The SmartDV's MIPI DPI Verification IP is fully compliant with version 2.0 MIPI Alliance specification and provides the following features.
MIPI DPI VIP is supported natively in Verilog and VHDL
- Supports 2.0 MIPI DPI Specifications.
- Supports Type 2, Type 3 and Type 4 Architecture.
- Supports programming display parameters
- Error Injection
- Supports reading of video pixel data from file
- Supports 16-bit,18-bit and 24 bits
- Have ability to control each and every timing parameters
- Callback in BFM and Monitor for wide range of events to help execute user code.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Status counters for various events in bus.
- MIPI DPI Verification IP comes with complete testsuite to test every feature of MIPI DPI specification.
- Functional coverage for complete MIPI DPI features.
- Faster testbench development and more complete verification of MIPI DPI designs.
- Easy to use command interface simplifies testbench control and configuration of Host, Display and Monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- MIPI DPI Verification Env
SmartDV's MIPI DPI Verification env contains following.
- Complete regression suite containing all the MIPI DPI testcases.
- Examples showing how to connect various components, and usage of Host, Display and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.