The Gigabit Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 1G Ethernet interface GMII. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.
GMII Ethernet SERDES VIP is supported for VMM, RVM, AVM, OVM and non-standard verification env
Features
Follows GMII specification as defined in IEEE 802.3.
Supports all types of GMII TX and RX errors insertion/detection.
Comes with GMII Tx BFM, GMII Rx BFM, and GMII Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.
Benefits
Faster testbench development and more complete verification of GMII designs.
Easy to use command interface simplifies testbench control and configuration of GMII TX and RX.
