Serial Peripheral Interface VIP

SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI basic protocol as defined in Motorola's M68HC11 user manual rev 5.0. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

Serial Peripheral Interface VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

 

Features

  • Follows SPI basic specification as defined in SPI Block Guide V04.01
  • Support Master and Slave Mode
  • Supports 3-wire,4-wire interface
  • Supports SQI interface specification and common flash device models
  • Supports data width from 4 bits to 64 bits.
  • Supports bus width 1 bit and 4 bit
  • Slave device supported for SPI 3 wire are
    • BOSCH SMB380
    • RICOH R2033K
  • Support baud rate selection
  • Support internal clock division check.
  • Support clock polarity selections.
  • Support CPHA selection.
  • Support single and burst transfer mode.
  • Support on the fly generation of data.
  • Detects and reports the following errors.
    • Mode Fault error
  • Supports constraints Randomization.
  • Glitch insertion and detection
  • Built in functional coverage analysis.
  • Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI bus.
  • SPI Slave can be configured as standard device or can use FIFO for data passing.
  • In standard model mode, Mater/Slave support different types of devices. Like FLASH, EEPROM, FRAM,RTC,SQI,MOTOROLA Mode,NS mode and TI mode(Precede and Coincide).
  • Master contains rich set of commands for both standard device and FIFO model mode.

Benefits

  • Faster testbench development and more complete verification of SPI designs.
  • Easy to use command interface simplifies testbench control and configuration of slave and master.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
 

SPI Verification Env

SmartDV's SPI Verification env contains following.

  • Complete regression suite containing all the SPI testcases.
  • Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

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