eMMC VIP

eMMC VIP

eMMC VIP is an advanced solution in the market for the verification of eMMC implementations. It is adherent with eMMC standard JESD84-B45. It can generate all command types. The eMMC VIP monitor acts as powerful protocol-checker, fully compliant with eMMC JESD84-B45 specification.

eMMC JESD84-B45 includes extensive test suite covering most of the possible scenarios and eMMC conformance norms. eMMC JESD84-B45 VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.

eMMC VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Compliant with eMMC JESD84-B45 specification.
• Single byte, single block, multiple block (finite and infinite) transfers.
• Supoorts stream transfer operations.
• Supports three different data width bus modes
• 1-bit(default)
• 4-bit
• 8-bit
• Supports boot opeartion mode with simple boot sequence method.
• Supports alternative boot operation mode
• Supports password protection of data
• Supports simple erase mechanism .
• Supports higher than 2GB of density of memories.
• Supports dual data rate transfer.
• Supports high speed boot.
• Supports hardware reset signal
• Supports write protection features for the boot and user areas, which may be permanent, power-on or temporary
• Tracking of the transmit and receive counters.
• Protocol Checker fully compliant with eMMC JESD84-B45 Specification.
• Functional coverage for complete JESD84-B45.
• Complete testsuite.
• Detects and reports the following errors.
• Out of range error
• Address misalign error
• CRC error
• Switch error
• Illegal command error
• Block length error
• Lock-unlock failed error
• Erase sequence error
• Direction bit error
• Stuff bit error
• Supports constraints Randomization.
• Configurable as agent (frame generator) or monitor.
• Bus-accurate timing.
• Monitor, Detects and notifies the testbench of all protocol errors.

Benefits

• Faster testbench development and more complete verification of eMMC designs.
• Easy to use command interface simplifies testbench control and configuration of slave and host.
• Simplifies results analysis.
• Runs in every major simulation environment.

eMMC Verification Env

SmartDV's eMMC Verification env contains following.

• Complete source code of slave, host and monitor
• Complete regression suite containing all the eMMC testcases.
• Examples's showing how to connect various components, and usage of Host, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.

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