Interlaken VIP

Interlaken VIP

The Interlaken Verification IP is compliant with 1.2 specifications and verifies Interlaken interfaces of designs Interlaken Interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Interlaken VIP is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Interlaken VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Follows Interlaken specification as defined in Interlaken protocol definition v1.2.
• Supports Interlaken look aside protcol specification v1.0
• Supports Interlaken retransmission extension specification 1.1
• Supports multi-channel implementation as per the specification.
• Supports configurable number of serial lanes as per the specification.
• Supports configurable burst max and burst short sizes.
• Supports insertion of extra idle to guarantee the avoidance of burst short.
• Supports scheduling calendar logic in the transmitter to choose the order in which the channels are serviced.
• Supports optional scheduling enhancement to avoid unused bandwidth by using decision algorithm.
• Each burst of transmitting data is encapsulated with burst control words before and after the data.
• Supports configurable metaframe length.
• Supports per channel inband and out of band flow control or both.
• Per-lane CRC-32 insertion into diagnostic words.
• Per lane skew insertion to test lane alignment.
• Configurable control to enable or disable the scrambler.
• 64B/67B encoding with inversion bits controllable.
• Supports very flexible way to test sync and alignment for state machines at startup.
• Following error injection is supported
• Receive SerDes loses lock
• Receive logic loses word boundary sync
• Bad scrambler state
• Lane alignment failure
• Burst CRC24 Errors
• Flow Control Errors
• Unknown Control Word Types
• Bad 64B/67B Code words
• Diagnostic CRC32 Errors
• All types of CRC error injection
• Invalid coding for all control words
• Error injection in metaframes
• Short burst error injection
• Invalid burst boundary
• Comes with Interlaken Tx BFM, Interlaken Rx BFM, and Interlaken Monitor.
• Supports Interlaken interop recommendations 1.3 and 1.4.
• Rich set of configuration parameters to control Interlaken functionality.
• Supports 67 bit bus per lane or 1 bit serial lane to ease the debugging.
• Supports 32,20,16,10 and 8 bit serdes interface bus.
• On-the-fly protocol and data checking.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• Complete functional coverage for both normal and error cases.
• Callbacks in Transmit, receiver and monitor for various events.
• Status counters for various events on bus.
• Interlaken Verification IP comes with complete testsuite to test every feature of Interlaken protocol specification.

Benefits

• Faster testbench development and more complete verification of Interlaken designs
• Easy to use command interface simplifies testbench control and configuration of Interlaken TX and RX
• Simplifies results analysis
• Runs in every major simulation environment

Interlaken Verification Env

SmartDV's Interlaken Verification env contains following.

• Complete source code of bfm and monitor
• Complete regression suite containing all the testcases.
• Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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