XLGMII 40G Ethernet VIP

XLGMII 40G Ethernet VIP

The 40G Ethernet Verification IP is compliant with IEEE 802.3ba specifications and verifies MAC-to-PHY layer interfaces of designs with a 40G Ethernet interface XLGMII. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet VIP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

XLGMII 40G Ethernet VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Follows XLGMII specification as defined in IEEE 802.3ba
• Supports all types of XLGMII TX and RX errors insertion/detection
• Oversize, undersize, inrange, out of range Packet size errors
• Missing SPD/EPD/SFD framing errors
• CRC Error
• Variable preamble and IPG insertion
• Invalid /D/ and /K/ character injection
• Comes with XLGMII Tx BFM, XLGMII Rx BFM, and XLGMII Monitor
• Monitor supports detection of all protocol violations
• Supports Pause frame generation and detection
• Built in coverage analysis
• Callbacks in master and slave for various events
• Status counters for various events in bus

Benefits

• Faster testbench development and more complete verification of XLGMII designs
• Easy to use command interface simplifies testbench control and configuration of XLGMII TX and RX
• Simplifies results analysis
• Runs in every major simulation environment

XLGMII 40G Ethernet Verification Env

SmartDV's XLGMII Verification env contains following.

• Complete source code of bfm and monitor.
• Complete regression suite containing all the testcases.
• Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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