The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 8b/10b PCS. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.
10G TBI Ethernet VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Follows 10G specification as defined in IEEE 802.3ae.
Supports all types of 8b/10b PCS TX and RX errors insertion/detection.
Comes with 8b/10b PCSI Tx BFM, 8b/10b PCS Rx BFM, and 8b/10b PCS Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.
Benefits
Faster testbench development and more complete verification of 10G 8b/10b designs.
Easy to use command interface simplifies testbench control and configuration of 10G 8b/10b TX and RX.
