MIPI SPMI VIP

MIPI SPMI VIP

MIPI SPMI Verification IP provides an smart way to verify the MIPI SPMI bi-directional two-wire bus. The SmartDV's MIPI SPMI Verification IP is fully compliant with version 1.0 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.

MIPI SPMI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Supports 1.0 MIPI SPMI Specification.
• Full MIPI SPMI Master and Slave functionality.
• Operates as a Master, Slave, or both.
• Monitor, Detects and notifies the testbench of all protocol and timing errors.
• Supports all topologies as per the MIPI SPMI specification
• Supports multiple slaves and multiple masters
• Support bus arbitration and bus arbitration error handling
• Supports following master bus connecting on bus
• Connecting by detecting SSC
• Connecting by detecting Bus idle
• Connecting by detecting Bus arbiration
• Slave is capable of bus arbitration
• Supports all types of SPMI commands
• Various kind of Master and Slave errors generation
• Undefined command frame
• Command frame with parity error
• Command frame length error
• Address frame with parity error
• Data frame with parity error
• Read of unused register
• Write of an unused register
• Read using the broadcast ID or a GSID
• Glitch monitor and injection.
• Support injection of glitch at all positions of SDATA
• Support injection of glitch at all positions of SCLK
• Supports detection of glitches
• Supports extended register read/writes
• Supports optional signal also
• Bus-accurate timing
• Supports half speed
• Callbacks in master and slave for various events.
• Status counters for various events in bus.

Benefits

• Faster testbench development and more complete verification of MIPI SPMI designs.
• Easy to use command interface simplifies testbench control and configuration of master, slave and monitor
• Simplifies results analysis.
• Runs in every major simulation environment.

MIPI SPMI Verification Env

SmartDV's MIPI SPMI Verification env contains following.

• Complete source code of MIPI SPMI Monitor, Slave, Master.
• Complete regression suite containing all the MIPI SPMI testcases.
• Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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