The 10G XAUI Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 10G XAUI. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.
10G XAUI Ethernet VIP is supported for VMM, RVM, AVM, OVM and non-standard verification env
Features
Follows 10G XAUI specification as defined in IEEE 802.3ae.
Supports all types of 10G XAUI TX and RX errors insertion/detection.
Comes with 10G XAUI Tx BFM, 10G XAUI Rx BFM, and 10G XAUI Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.
Benefits
Faster testbench development and more complete verification of 10G XAUI designs.
Easy to use command interface simplifies testbench control and configuration of 10G XAUI TX and RX.
