10G XAUI/10GBase-KX4/KR Ethernet VIP

The 10G XAUI/10GBase-KX4/KR Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 10G XAUI. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.

10G XAUI/10GBase-KX4/KR Ethernet VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

 

Features

  • Follows 10G XAUI specification as defined in IEEE 802.3ae.
  • Supports 10GBase-KR and 10Gbase-KX4 specs.
  • Supports all types of 10G XAUI TX and RX errors insertion/detection.
  • Comes with 10G XAUI Tx BFM, 10G XAUI Rx BFM, and 10G XAUI Monitor
  • Monitor supports detection of all protocol violations.
  • Supports Pause frame generation and detection.
  • Built in coverage analysis.

    • Benefits

  • Faster testbench development and more complete verification of 10G XAUI designs.
  • Easy to use command interface simplifies testbench control and configuration of 10G XAUI TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
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    10G XAUI Verification Env

    SmartDV's 10G XAUI Verification env contains following.

    • Complete SystemVerilog source code of 10G XAUI Monitor, TX and RX BFM.
    • Complete regression suite (UNH) containing all the 10G XAUI testcases.
    • Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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