IEEE 1149.7 CJTAG Verification IP provides an smart way to verify the IEEE 1149.7 CJTAG component of a SOC or a ASIC. The SmartDV's IEEE 1149.7 CJTAG Verification IP is fully compliant with standard IEEE 1149.7 CJTAG Standard and provides the following features.
IEEE 1149.7 CJTAG VIP is supported natively in Verilog and VHDL
- Fully compatible with IEEE 1149.7 CJTAG standard.
- Can be used as TAP controller (slave) or TAP instruction/data generator (Master) for CJTAG.
- Comes with CJTAG monitor to check and report any protocol violation.
- Supports extended protocol unit (EPU) for classes 1 to 3
- Supports all mandatory and optional EPU commands
- Supports advanced protocol unit (APU) for classes 4 and 5
- Supports 4 and 2 pin operation as specified in IEEE 1149.7 CJTAG
- Supports all mandatory and optional scan formats (Jscan, MScan, OScan, and SScan)
- Can be extended with user defines instructions and registers.
- Supports optional reset signal.
- Supports functional coverage.
- On-the-fly protocol and data checking
- Callbacks support for BFM and Monitor.
- Faster testbench development and more complete verification of IEEE 1149.7 CJTAG designs.
- Easy to use command interface simplifies testbench control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- IEEE 1149.7 CJTAG Verification Env
SmartDV's IEEE 1149.7 CJTAG Verification env contains following.
- Complete regression suite containing all the IEEE 1149.7 CJTAG testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.