Ethernet VIP

The 10/100/1G/10G/40G/100G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1G/10G/40G/100G Ethernet interface. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog. Ethernet VIP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

Ethernet VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

 

Features

  • Supports MII/GMII/RMII/RGMII/RTBI/TBI/SMII/SGMII/1000Base-KX
  • Supports XGMII/XTBI/XAUI/10GBase-KR/10GBase-KX4
  • Supports 64/66 bits protocol, for debugging KR at 64 or 66 bit interface with/without scrambler
  • Supports XLGMII/40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4 for 40G
  • Supports CLGMII/100GBase-KR10/100GBase-CR10/100GBase-SR10/100GBase-ER4/100GBase-LR4 for 100G
  • Supports FEC for 10G,40G and 100G
  • Follows 802.3 2008 version
  • Follows RGMII specification 2.0
  • Follows RMII specification 1.2
  • Follows SGMII specification 1.8
  • Follows SMII specification 2.1
  • Follows P8023ba for 40G and 100G
  • Support MDIO slave and master model
  • Supports all types of TX and RX errors insertion/detection at each layer.
  • Comes with Tx BFM, Rx BFM, and Monitor
  • Monitor supports detection of all protocol violations
  • Supports Pause frame generation and detection
  • Built in coverage analysis
  • Callbacks in master and slave for various events
  • Status counters for various events in bus
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    Benefits

  • Faster testbench development and more complete verification of Ethernet designs
  • Easy to use command interface simplifies testbench control and configuration of TX and RX
  • Simplifies results analysis
  • Runs in every major simulation environment
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    MII/GMII Verification Env

    SmartDV's Ethernet Verification env contains following.

    • Complete SystemVerilog source code of Ethernet Monitor, TX and RX BFM.
    • Complete regression suite (UNH) containing all the Ethernet testcases.
    • Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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