Ethernet VIP

The 10/100/1G/10G/40G/100G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a 10/100/1G/10G/40G/100G Ethernet interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet VIP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

Ethernet VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

 

Features

  • Supports 100G as per 802.3ba
  • Supports 40G as per 802.3ba
  • Supports 10G as per 802.3
    • Supports XGMII
    • Supports XTBI (i.e Output of 8b/10b PCS)
    • SUpports XAUI and 10GBASE-KX4
    • Supports 10GBASE-KR with scrambler
    • Supports FEC for 10GBase-KR
    • Supports scrambler
    • Supports backplane auto-negotation for 10GBase-KX4 and 10GBase-KR
  • Supports 1G
    • Supports GMII
    • Supports TBI (i.e Output of 8b/10b PCS)
    • Supports SGMII as per specification 1.8
    • Supports RGMII/RTBI as per specification 2.0
    • Supports 1000Base-KX
    • Supports clause 73 backplane auto-negotation for 1000Base-KX
    • Supports clause 37 auto-negotation
    • Supports SGMII auto-negotation
    • Supports full duplex and half duplex of operation
  • Supports 100M
    • Supports MII
    • Supports SMII as per specification 2.1
    • Supports RMII as per specification 1.2
  • Support MDIO slave and master model
  • Supports all types of TX and RX errors insertion/detection at each layer.
  • Comes with Tx BFM, Rx BFM, and Monitor
  • Monitor supports detection of all protocol violations
  • Supports Pause frame generation and detection
  • Built in coverage analysis
  • Callbacks in master and slave for various events
  • Status counters for various events in bus

Benefits

  • Faster testbench development and more complete verification of Ethernet designs
  • Easy to use command interface simplifies testbench control and configuration of TX and RX
  • Simplifies results analysis
  • Runs in every major simulation environment
 

Ethernet Verification Env

SmartDV's Ethernet Verification env contains following.

  • Complete source code of bfm and monitor
  • Complete regression suite (UNH) containing all the Ethernet testcases.
  • Examples's showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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