The 10G Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface XGMII. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.
XGMII Ethernet VIP is supported for VMM, RVM, AVM, OVM and non-standard verification env
Features
Follows XGMII specification as defined in IEEE 802.3ae.
Supports all types of XGMII TX and RX errors insertion/detection.
Comes with XGMII Tx BFM, XGMII Rx BFM, and XGMII Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.
Benefits
Faster testbench development and more complete verification of XGMII designs.
Easy to use command interface simplifies testbench control and configuration of XGMII TX and RX.
