IEEE 1149.1 (JTAG) VIP
IEEE 1149.1 (JTAG) Verification IP provides an smart way to verify the IEEE 1149.1 (JTAG) component of a SOC or a ASIC. The SmartDV's IEEE 1149.1 (JTAG) Verification IP is fully compliant with standard IEEE 1149.1 (JTAG) Standard and provides the following features.
IEEE 1149.1 (JTAG) VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
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Features
Fully compatible with IEEE 1149.1 (JTAG) standard.
Can be used as TAP controller (slave) or TAP instruction/data generator (Master).
Comes with JTAG monitor to check and report any protocol violation.
Supports mandatory instruction in IEEE 1149.1, BYPASS, SAMPLE, PRELOAD and EXTEST
Supports optional instructions in IEEE1149.1, IDCODE, USERCODE, CLUMP and HIGHZ.
Can be extended with user defines instructions and registers.
Supports optional reset signal.
Supports functional coverage.
On-the-fly protocol and data checking
Callbacks support for BFM and Monitor.
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Benefits
Faster testbench development and more complete verification of IEEE 1149.1 (JTAG) designs.
Easy to use command interface simplifies testbench control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.
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IEEE 1149.1 (JTAG) Verification Env
SmartDV's IEEE 1149.1 (JTAG) Verification env contains following.
- Complete SystemVerilog, Vera source code of IEEE 1149.1 (JTAG) Monitor and BFM.
- Complete regression suite containing all the IEEE 1149.1 (JTAG) testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
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