SDIO VIP
SDIO 1.0 and 2.0 VIP is an advanced solution in the market for the verification of SDIO 1.0/2.0 implementations. It is adherent with SDIO 1.0/2.0 VIP and it supports SPI, SD1, SD4 and MMC8. It can generate all command types. The SDIO VIP monitor acts as powerful protocol-checker, fully compliant with SDIO 1.0/2.0 specification. SDIO 1.0/2.0 VIP includes an extensive test suite covering most of the possible scenarios and SDIO conformance norms. SDIO 1.0/2.0 VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.
SDIO VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
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Features
SD Host Specification 1.0 compliant, SD Specification 2.00 and SDIO Specification 2.0 Draft compliant.
Supports SDIO, SD Memory, SD Combo card and Multi-media cards
Supports single slot operation
Easily configurable to work as SDIO aware or non-SDIO aware host controller
Card detection on DAT [3] line in SD mode and CS line in SPI mode
Re-initializing of combo card in either SDIO only mode or SD memory only mode
Command level features such as resetting the card, setting bus width and changing bus mode (SD to SPI)
1-bit, 4-bit, 8-bit (for MMC Only) SD bus mode and SPI bus mode
Low speed mode, full speed mode and high speed mode operations
Single byte, single block, multiple block (finite and infinite) transfers
MMC stream transfer operations
Direct command during data transfer (SD mode only)
Read wait operation and allows read wait control by stopping clock and by asserting DAT [2] line low
Asynchronous and synchronous abort mechanism
Suspend/Resume card operation
SD 1-bit, SPI mode interrupt and SD 4-bit mode card interrupts
Lock-unlock and erase operation card features
Clock disable and interrupt wake up card features
Tracking of the transmit and receive counters.
Protocol Checker fully compliant with SD Host Specification 1.0 compliant, SD Specification 2.00 and SDIO Specification 2.0 Draft compliant.
Functional Coverage Measure.
Complete testsuite
Configurable as agent (frame generator) or monitor.
Compares read data with expected results
Bus-accurate timing
Monitor, Detects and notifies the testbench of all protocol errors.
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Benefits
Faster testbench development and more complete verification of SDIO designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.
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SDIO Verification Env
SmartDV's SDIO Verification env contains following.
- Complete SystemVerilog source code of SDIO Monitor, Slave, Host.
- Complete regression suite containing all the SDIO testcases.
- Examples's showing how to connect various components, and usage of Host, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
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