SDIO 3.0 VIP
SDIO 1.0, 2.0 and 3.0 VIP is an advanced solution in the market for the verification of SDIO 1.0/2.0/3.0 implementations. It is adherent with SDIO 1.0/2.0/3.0 VIP and it supports SPI, SD1, SD4 and MMC8. It can generate all command types. The SDIO VIP monitor acts as powerful protocol-checker, fully compliant with SDIO 1.0/2.0/3.0 specification.
SDIO 1.0/2.0/3.0 VIP includes an extensive test suite covering most of the possible scenarios and SDIO conformance norms. SDIO 1.0/2.0/3.0 VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.
SDIO 3.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- SDIO Specification 1.0/2.0/3.0 compliant.
- Supports SDIO, SD Memory, SD Combo card and Multi-media cards.
- Easily configurable to work as SDIO aware or non-SDIO aware Host controller.
- Card detection on DAT  line in SD mode and CS line in SPI mode.
- Re-initialization of combo card in either SDIO only mode or SD memory only mode.
- Command level features such as resetting the card, setting bus width and changing bus mode (SD to SPI).
- 1-bit, 4-bit, 8-bit SD bus mode and SPI bus mode.
- Supports read-write, read-only cards
- All version 3.0 features supported such as speed class, tuning, voltage and block size control.
- Supports capacity of Memory
- Switch function command supports Bus speed mode,command system,drive strength & future function
- Set block count(CMD23) command is supported
- Supports different memory capacities given below:
- Standard Capacity SD Memory Card (SDSC) : Up to and including 2 GB
- High Capacity SD Memory Card (SDHC) : More than 2GB and up to and including 32GB
- Extended Capacity SD Memory Card (SDXC) : More than 32GB and up to and including 2TB
- All UHS1 modes – SDR50/SDR104/DDR50.
- Supports e-MMC standard and high capacity standards JESD840A42 and JESD84-B45, Supports MMC standard JESD840B42.
- Low speed mode, full speed mode and high speed mode operations.
- Single byte, single block, multiple block (finite and infinite) transfers, MMC stream transfer operations.
- Direct command during data transfer (SD mode only).
- Read wait operation and allows read wait control by stopping clock and by asserting DAT  line low.
- Supports all features of SDIO card type-A specification for bluetooth version 1.00
- Supports all features of SDIO card type-B specification for bluetooth version 1.00
- Supports all features of SD specification Part1 eSD(Embedded SD) addendum version 2.10
- Supports all features of write protect feature
- Supports application specific commands
- Asynchronous and synchronous abort mechanism.
- Suspend/Resume card operation.
- Lock-unlock and erase operation card features.
- SD 1-bit , SPI mode interrupt and SD 4-bit mode card interrupts.
- Clock disable and interrupt wake up card features.
- Tracking of the transmit and receive counters.
- Detects and reports the following errors.
- Out of range error
- Address misalign error
- CRC error
- Switch error
- Illegal command error
- Block length error
- Lock-unlock failed error
- Erase sequence error
- Direction bit error
- Stuff bit error
- Erase param error
- Parameter error
- Reserved bit error
- Invalid voltage error
- Function number error
- CSD/CID overwrite error
- WP violation error
- Protocol Checker fully compliant with SDIO Specification 1.0/2.0/3.0 compliant.
- Functional coverage for complete SDIO Specification 1.0/2.0/3.0 compliant.
- Supports constraints Randomization.
- Callbacks in host, slave and monitor for user processing of data.
- Complete testsuite to verify each and every feature of SDIO standard.
- Configurable as agent (frame generator) or monitor.
- Bus-accurate timing.
- Status counters for various events on bus
- Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Faster testbench development and more complete verification of SDIO designs.
- Easy to use command interface simplifies testbench control and configuration of slave and host.
- Simplifies results analysis.
- Runs in every major simulation environment.
SDIO Verification Env
SmartDV's SDIO Verification env contains following.
- Complete source code of bfm and monitor
- Complete regression suite containing all the SDIO testcases.
- Examples's showing how to connect various components, and usage of Host, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
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