Features
Supports DDR3 memory devices from all leading vendors
Quickly validates the implementation of the DDR3 standard
Constantly monitors DDR3 behavior during simulation
Checks for following
- Check-points include Initialization rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
Support for full-timing as well as behavioral versions in one model
Support for all timing delay ranges in one model: min, typical and max
Supports Callbacks, so that user can access the data observed by monitor.
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Benefits
Faster testbench development and more complete verification of DDR3 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.
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