AMBA5 CHI Assertion IP provides an smart way to verify the ARM AMBA5 CHI component of a SOC or a ASIC. The SmartDV's AMBA5 CHI Assertion IP is fully compliant withstandard AMBA5 CHI Specification and provides the following features.
AMBA5 CHI AIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Features
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- Specification Compliance
- Compliant with the latest ARM AMBA5 CHI specification.
- Supports all ARM AMBA5 CHI data widths.
- Supports for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
- Supports all CHI protocol node types:
- Request Nodes (RN-F, RN-D and RN-I)
- Home Nodes (HN-F, HN-I and MN)
- Slave Nodes (SN-F and SN-I)
- configurable support for snoop broadcast vector.
- Support for Speculative read and Snoop filtering.
- Support for all Transaction types/Opcodes including Barrier, DVM and Exclusive access.
- Support for Request transactions with/without a Retry of transactions.
- Assertion IP features
- AIP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode and Monitor mode.
- Supports Simulation mode (stimulus from SmartDV CHI VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure CHI AIP functionality.
- Benefits
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- Runs in every major simulation environment.
- AMBA5 CHI Assertion Env
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SmartDV's AMBA5 CHI Assertion env contains following.
- Detailed documentation of all class, task and function's used in assertion env.
- Documentation also contains User's Guide and Release notes.
