SPDIF VIP

SPDIF VIP

SPDIF Verification IP provides an smart way to verify the SPDIF component of a SOC or a ASIC. The SmartDV's SPDIF Verification IP is fully compliant with IEC 60958 Specification and provides the following features.

SPDIF VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Full SPDIF functionality.
• Configurable Baud rate control.
• Supports the Biphase-mark code
• Supports injection of various of errors
• Biphase-mark encoding error
• Preamble error
• Channel encoding error
• Channel status error
• Parity Error
• Various field errors
• FIFO depth programmable.
• Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
• Supports constraints Randomization.
• Callbacks in transmitter, receiver and monitor for user processing of data.
• Functional coverage for complete SPDIF IEC 60958 features.
• SPDIF Verification IP comes with complete testsuite to verify each and every feature of SPDIF specification.
• On-the-fly protocol and data checking

Benefits

• Faster testbench development and more complete verification of SPDIF designs.
• Easy to use command interface simplifies testbench control and configuration of TX and RX.
• Simplifies results analysis.
• Runs in every major simulation environment.

SPDIF Verification Env

SmartDV's SPDIF Verification env contains following.

• Complete source code of Tx,Rx and monitor.
• Complete regression suite containing all the SPDIF testcases.
• Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.

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