JESD204 VIP

JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC. JESD204 VIP can be used to verify transmitter or Receiver device following the JESD204 basic protocol as defined in JESD204. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

JESD204 VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

 

Features

  • Follows JESD204 specification as defined in JESD204a
  • Support transmitter and Receiver Mode
  • Supports upto 32 serial lanes
  • Supports upto 32 converters per transmitter and Receiver BFM
  • Supports upto 64 bits of data width per coverter
  • Supports lane skew insertion in transmitter mode
  • Supports disparity and invalid code insertion in 8b/10b
  • Supports scrambler as in JESD204 specification
  • Support on the fly generation of data.
  • Detects and reports the following errors.
  • Built in coverage analysis.

    • Benefits

  • Faster testbench development and more complete verification of JESD204 designs.
  • Easy to use command interface simplifies testbench control and configuration of slave and master.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
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    JESD204 Verification Env

    SmartDV's JESD204 Verification env contains following.

    • Complete SystemVerilog source code of JESD204 Monitor, Receiver, Transmitter.
    • Complete regression suite containing all the JESD204 testcases.
    • Examples's showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.




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