JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC. JESD204A/B VIP can be used to verify transmitter or Receiver device following the JESD204 basic protocol as defined in JESD204. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
is supported natively in Verilog and VHDL
- Follows JESD204A/B specification as defined in JESD204A/B.
- Supports Transmitter and Receiver Mode.
- Supports up to 32 lanes.
- Supports 32bit data width per converter.
- Supports up to 32 converters per transmitter & receiver BFM.
- Scrambler can be enabled or disabled.
- Supports disparity & invalid code insertion in 8b/10b.
- Supports sync error injection.
- Supports lane skew insertion.
- Supports scrambler error injection.
- Supports constraints Randomization.
- Functional coverage to cover each and every feature of the JESD204 specification.
- Test suite to test each and every feature of JESD204 specification.
- Callbacks in Transmitter and Receiver for various events.
- Status counters for various events on bus.
- Faster testbench development and more complete verification of JESD204B designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- JESD204B Verification Env
SmartDV's JESD204B Verification env contains following.
- Complete regression suite containing all the JESD204 testcases.
- Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.