MIPI DPHY Verification IP

MIPI DPHY VIP

MIPI DPHY Verification IP is compliant with MIPI UNIPRO specification and verifies UNIPRO devices. UNIPRO Verification IP is developed by experts who have worked on complex protocols before.

MIPI DPHY VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

Supports 1.0 MIPI DPHY Specification.
Supports up to four D-PHY lanes
Supports various kind of Tx and Rx errors generation and detection on D-PHY

SoT error
Sync error
Sync length error
Ecc error

Supports PPI interface
Supports both short and long packets
Supports 8b/9b coding
Supports BTA operation and error injection in BTA
Supports detection of all timeouts and injection of various timeout errors
Supports both high speed and low power packet transmission and reception
Supports fine grain control of timing parameters
Monitor,Detects and notifies the testbench of all protocol and timing errors.
Supports constraints Randomization.
Status counters for various events in bus.
Callbacks in transmitter and receiver for various events.
MIPI DPHY Verification IP comes with complete test suite to test every feature of MIPI DPHY specification.
Functional coverage for complete MIPI DPHY features.

Benefits

Faster testbench development and more complete verification of MIPI DPHY designs.
Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
Simplifies results analysis.
Runs in every major simulation environment.

MIPI DPHY Verification Env

SmartDV's MIPI DPHY Verification env contains following.

Complete source code of BFM and monitor.
Complete regression suite containing all the MIPI DPHY testcases.
Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

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