SmartDV VByOneHS Verification IP

V-By-One HS VIP

V-By-One HS is the serial communication protocol developed by Thine Electronics, Inc to support the higher frame rates and the higher resolutions required by advancing FPD technologies. V-By-One HS VIP can be used to verify transmitter or Receiver device following the V-By-One HS basic protocol as defined in V-By-One HS. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

V-By-One HS VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env

Features

Follows V-By-One HS specification as defined in V-By-One HS version 1.2

Support transmitter and Receiver Mode

Supports upto 32 serial lanes

Supports lane skew insertion in transmitter mode

Supports disparity and invalid code insertion in 8b/10b

Supports scrambler as in V-By-One HS specification

Support on the fly generation of data.

Detects and reports the following errors.

Built in coverage analysis.

Benefits

Faster testbench development and more complete verification of V-By-One HS designs.

Easy to use command interface simplifies testbench control and configuration of slave and master.

Simplifies results analysis.

Runs in every major simulation environment.

V-By-One HS Verification Env

SmartDV's V-By-One HS Verification env contains following.

Complete SystemVerilog source code of V-By-One HS Monitor, Receiver, Transmitter.
Complete regression suite containing all the V-By-One HS testcases.
Examples's showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.