MIPI SPMI Slave interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI SPMI Slave IIP is proven in FPGA environment.The host interface of the MIPI SPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

MIPI SPMI SLAVE IIP is supported natively in Verilog, VHDL and SystemC



  • Supports 2.0 and 1.0 MIPI SPMI Specification
  • Full MIPI SPMI Slave functionality
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports ACK/NAK as per 2.0 specs
  • Support for slave requests through Alert bit.
  • Support for slave request hold.
  • Glitch suppression (optional).
  • Supports extended register read/writes
  • Supports wakeup command
  • Supports Authentication Command Sequence
  • Device Descriptor Block command Sequences
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Slave IP can be build to have additional slave interface blocks like SPI or I2C, in addition to SPMI slave functionality.

Licensing Options

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.


  • SmartDV's MIPI Slave IP contains following.
  • The MIPI Slave interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.

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