SMBUS VIP

SMBUS VIP

SMBus Verification IP provides an smart way to verify the SMBus bi-directional two-wire bus. The SmartDV's SMBus Verification IP is fully compliant with version 2.0 of the SMBus Specification and provides the following features.

SMBUS VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Supports SMBus specification version 2.0
• Supports all SMBus device types: Master, Slave
• Supports all SMBus command protocols
• Supports packet error checking
• Supports ARP sequence
• Performs error injection
• Master aborting in middle of access
• Master doing ACK on last read access
• Master continue after NAC from slave for write data
• Glitch injection on clock and data at various windows
• PEC error
• ACK for PEC field by master for read data
• Wrong ARP commands
• Unsupported command codes
• Illegal commands lengths
• Generates and handles glitches generating on both SMBDAT and SMBCLK lines
• Supports timeouts forcing and handling
• Supports scoreboard checking
• Built-in monitors for protocol checking, including a global bus monitor
• Functional coverage to cover all functionality of SMBus slave and master
• Support for multiple instantiations to create complex verification environment

Benefits

• Faster testbench development and more complete verification of SMBUS designs.
• Easy to use command interface simplifies testbench control and configuration of slave and master.
• Simplifies results analysis.
• Runs in every major simulation environment.

SMBUS Verification Env

SmartDV's SMBUS Verification env contains following.

• Complete source code of SMBUS Monitor and BFM.
• Complete regression suite containing all the SMBus testcases to certify SMBus slave/master device
• Examples's showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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