SMBus Verification IP provides an smart way to verify the SMBus bi-directional two-wire bus. The SmartDV's SMBus Verification IP is fully compliant with version 2.0 of the SMBus Specification and provides the following features.
SMBUS VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Supports SMBus specification version 2.0
Supports all SMBus device types: Master, Slave
Supports all SMBus command protocols
Supports packet error checking
Supports ARP sequence
Performs error injection
Generates and handles glitches generating on both SMBDAT and SMBCLK lines
Supports timeouts forcing and handling
Supports scoreboard checking
Built-in monitors for protocol checking, including a global bus monitor
Built-in coverage analysis for all transactions types
Support for multiple instantiations to create complex verification environment
Benefits
Faster testbench development and more complete verification of SMBUS designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
