RapidIO VIP
RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus. The SmartDV's RapidIO Verification IP is fully compliant with version 1.3 and 2.0 of the RapidIO Specification and provides the following features.
RapidIO VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
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Features
Supports RapidIO specification 1.3 and 2.0
Support Serial 1x/4x Physical lanes.
Supports 3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s
66, 50, or 34-bit addressing on the RapidIO interface
Support of Error Management Extensions.
Supports Parallel Physical interface.
Supports all types of packets and sizes.
Supports I/O system, message passing and globally shared distributed memory (GSM) Logical Layer architectures
Supports generation and reaction to flow control.
Supports creating of error conditions at each layer of RapidIO.
Very flexible to insert errors in Serial lanes.
Support all types of timing and protocol violation detection.
Supports callbacks for user to get packets or errors in INITIATOR/TARGET and monitor.
Functional coverage for each functional condition in env.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
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Benefits
Faster testbench development and more complete verification of RapidIO designs.
Easy to use command interface simplifies testbench control and configuration of TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.
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RapidIO Verification Env
SmartDV's RapidIO Verification env contains following.
- Complete Verilog or OpenVera or SystemVerilog source code of RapidIO Monitor, BFM.
- Complete regression suite containing all the RapidIO testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
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