I2S Synthesizable VIP provides an smart way to verify the I2S bi-directional two-wire bus. The SmartDV's I2S Synthesizable VIP is fully compliant with version 1.1 of the Philip's I2S-Bus Specification and provides the following features.
I2S Synthesizable VIP
is supported natively in Verilog and VHDL
- Complies with Philips I2S Specification version 1.1
- Full I2S Transmitter and Receiver functionality
- Supports up to 32 channels in transmit path
- Supports up to 32 channels in receive path
- Supports programmable word length 8,12,16,20,24,32
- Supports programmable padding
- Supports programmable bit rotate
- Supports programmable bit reversal
- Supports left and right justified
- Both transmitter and receiver can either work with SCK as input or can drive SCK
- Supports programmable data rate on transmit path
- Can operate as master or slave in several configurations
- - Master or slave mode as transmitter
- - Master or slave mode as receiver
- - Master mode as controller (does not transmit or receive data)
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Status counters for various events on bus.
- Callbacks in transmitter, receiver and monitor for various events.
- Supports constraints Randomization.
- Built in functional coverage analysis.
- I2S Verification IP comes with complete test suite to test every feature of I2S specification.
- Compatible with testbench writting using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment.
- Runs in custom FPGA platforms
- I2S Synthesizable VIP Env
SmartDV's I2S Synthesizable env contains following.
- Synthesizable transactors
- Complete regression suite containing all the UART testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.