USB 2.0 VIP

USB 2.0 VIP

USB Verification IP provides an smart way to verify the USB component of a SOC or a ASIC.It provides backward compatibility support for earliers versions of USB specifications. The SmartDV's USB Verification IP is fully compliant with standard USB Specification 1.0 and 2.0.

USB VIP data transfer can be done at differnt speeds. Which intuitively involves high speed (480Mbits/sec), fullspeed (12Mbits/sec) or low speed (1.5 Mbits/sec).The USB VIP includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.This way it detects the violation of protocol completely.

USB 2.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Compatible with USB 1.1, USB 2.0, USB OTG.
• Supports Standard USB 2.0 interface, UTMI, UTMI+, ULPI and HSIC interfaces.
• Standard DP/DM bus interface is supported.
• Operates at high, full and low speed.
• Support HOST and Device model.
• Supports up to 127 devices.
• Supports completely configurable bus enumeration.
• Supports all descriptor types and device requests.
• Supports Link Power Management (LPM).
• Supports constrained randomization of protocol attributes.
• All USB2.0 transfer types (Control, Isochronous, Interrupt, Bulk) are supported.
• Supports both transaction level (Setup, In, Out, Ping) and packet level (Token, Data, Handshake, SOF) transmission/reception.
• Constrained driven randomization of packets achieved by randomization of various fields of the packet.
• Auto detection of device connection and disconnection.
• Supports SRP and HNP compliance checking.
• Provides SOF generation support.
• Programmable inter packet and end-to-end delays.
• Proficiency to generate random packets/transactions and respond to packets/transactions in directed or randomized fashion.
• Supports all types of error injection and detection. Errors include:
• Corrupt Sync byte
• Corrupt PID Byte
• Corrupt CRC-5 Byte
• Corrupt CRC-16 Byte
• Corrupt Endpoint Address Byte
• Corrupt Setup Payload Size
• Corrupt Setup Stage Data Payload
• Corrupt EOP byte
• Bit stuffing error.
• Programmable timers for suspend, resume and reset signaling.
• On-the-fly protocol and data checking.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• Built in coverage analysis.
• Callbacks in host and device for various events.
• USB Verification IP comes with complete testsuite to test every feature of USB specification.

Benefits

• Rich set of configuration parameters to control the functionality
• Faster testbench development and more complete verification of USB designs.
• Easy to use command interface simplifies testbench control and configurationof device and host.
• Simplifies results analysis.
• Runs in every major simulation environment.

USB Verification Env

SmartDV's USB Verification env contains following.

• Complete source code of bfm and monitor.
• Complete regression suite containing all the USB testcases.
• Examples's showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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