USB Verification IP provides an smart way to verify the USB component of a SOC or a ASIC. The SmartDV's USB Verification IP is fully compliant with standard USB Specification 1.0 and 2.0a and provides the following features.
USB VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
Features
Compliant to USB Protocol
Compliant to USB Specification Revision 2.0
(1.1 compatible) & supports OTG supplement
to USB 2.0 Revision 1.0a
Support for all types of USB models :
Host
Device
Dual-role device
Supports D+/D-, UTMI & ULPI interfaces
Support all USB Protocol data and address width
Support all USB Protocol transfer types and response
Assertions and Checks for protocol violations
Logs and report for bus traffic
Also includes User-configurable commands
Call backs and call back variables to provide control over test case execution
On-the-fly protocol and data checking
Benefits
Faster testbench development and more complete verification of USB designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
Simplifies results analysis.
Runs in every major simulation environment.
USB Verification Env
SmartDV's USB Verification env contains following.
Complete SystemVerilog source code of USB Host, USB Device, USB Monitor and USB Checker.
Complete regression suite containing all the USB testcases.
Examples's showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.
