I2C/SMBus VIP

I2C/SMBus VIP

I2C/SMBus Verification IP provides an smart way to verify the I2C/SMBus bi-directional two-wire bus. The SmartDV's I2C/SMBus Verification IP is fully compliant with version 2.1 of the Philip's I2C-Bus Specification and SMBus 2.0 Specification and provides the following features.

I2C/SMBus VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Supports standard, fast, and high speed operations.
• Full I2C Master and Slave functionality.
• Supports packet error checking for SMBus mode
• Supports ARP sequence for SMBus mode
• Operates as a Master, Slave, or both.
• Monitor, Detects and notifies the testbench of all protocol and timing errors.
• Supports all I2C clocking speeds
• 7b/10b configurable slave address
• Compares read data with expected results
• Bus-accurate timing
• Various kind of Master and Slave errors generation
• Glitch monitor and injection.
• Supports timeouts forcing and handling in SMBus mode
• Callbacks in master and slave for various events.
• Status counters for various events in bus.

Benefits

• Faster testbench development and more complete verification of I2C/SMBus designs.
• Easy to use command interface simplifies testbench control and configuration of Master and Slave.
• Simplifies results analysis.
• Runs in every major simulation environment.

I2C Verification Env

SmartDV's I2C/SMBus Verification env contains following.

• Complete source code of I2C/SMBus Monitor, Slave, Master.
• Complete regression suite containing all the I2C/SMBus testcases.
• Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

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