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AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 VIP

AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 VIP

AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Verification IP provides an smart way to verify the ARM AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 component of a SOC or a ASIC. The SmartDV's AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Verification IP is fully compliant with standard AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Specification. Our AMBA AXI VIP is proved across multiple customers.

AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with the latest ARM AMBA5 AXI and ACE Protocol Specification.
  • Supports all protocols/interfaces AXI3/AXI4/AXI4-Lite/AXI4-Stream/AXI5/AXI5-Lite/ACE/ACE-Lite/ACE5/ACE5-Lite/ACE5-LiteDVM/ACE5-LiteACP.
  • Supports AXI Master, AXI Slave, AXI Interconnect, AXI Monitor and AXI Checker.
  • Supports all ARM AMBA AXI/ACE 3.0/4.0/5.0 data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address/control, data and response phases. Separate read, write and snoop channels.
  • Support for burst-based transactions with only start address issued.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • AXI3/AXI4/AXI5/ACE/ACE5 Common support
    • Write strobe support to enable sparse data transfer on the write data bus.
    • Narrow transfer support.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Write address independent response (Driving write data and providing response before address is accepted, after accepting all data).
    • Protected accesses with normal/privileged,secure/non-secure and data/instruction
    • Support for Write data phase before Write address phase (negative AWVALID to WVALID delay)
    • Ability to configure the width of all signals.
    • Support for conversion of different protocols and different data width.
    • Support for bus inactivity detection and timeout(configuration parameter and dynamic change of inactivity timer).
    • Configurable WID signal enable support for AXI4/ACE/ACE_LITE.
  • AXI3 support
    • Write data and read data interleaving support.
    • Configurable write and read interleave depth.
    • Programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Low-power Interface support
    • Atomic access support with normal access,exclusive access and locked access
  • AXI4 support
    • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Atomic access support with normal access and exclusive access
    • Longer bursts up to 256 beats.
    • Quality of Service signaling.
    • Multiple region interfaces.
    • User signaling support.
    • Ability to break longer bursts into multiple shorter bursts
    • Supports unmapped region address accesses
    • AWCACHE and ARCACHE Attributes.
    • Low-power Interface support
  • AXI4-Lite support
    • Burst length of 1.
    • Write strobe support.
    • Data bus width of 32-bit or 64-bit.
    • Ability to issue multiple outstanding transactions.
  • ACE support
  • In addition to AXI4 features, ACE supports the following features,
    • Supports functionality to verify ACE and CCI interconnect functionality for cache.
    • Supports all ACE transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
    • Support for multiple outstanding ACE transactions.
    • Supports all write/read responses and snoop responses.
    • Support for cache model and snoop filtering
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated snoop transaction to snooped Masters.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Fine grain control of Snooped Master’s response to a snoop transaction.
  • ACE-Lite support
  • ACE-Lite has all the support similar to ACE, complying with the Specification for ACE-Lite specific features.
    • Barrier transactions
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • AXI4-Stream support
    • Support for single byte, packet and frame transfers.
    • Support for all Data streams including Byte stream, Continuous aligned stream, Continuous unaligned stream and Sparse stream.
    • Transfer interleaving support.
    • Support for upsizing, downsizing and merging.
  • AMBA5 support
    • Atomic transactions.
    • Cache stashing.
    • Deallocating transactions.
    • Cache Maintenance for persistence.
    • Data Checking and Poison.
    • Trace Signals.
    • User Loopback Signaling.
    • Qos Accept signaling.
    • Wakeup Signaling mechanism.
    • Coherency Connection signaling
    • Distributed Virtual Memory extensions for ARMv8.1
    • Untranslated transactions
    • Non-secure access identifiers
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control AXI functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in master, slave, interconnect and monitor for various events.
  • Status counters for various events on bus.
  • AXI Verification IP comes with complete testsuite to test every feature of ARM AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 specification.
Benefits
  • Faster testbench development and more complete verification of AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Verification Env

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    SmartDV's AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Verification env contains following.

  • Complete regression suite containing all the AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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