AMBA 3 AXI VIP
AMBA 3 AXI Verification IP provides an smart way to verify the AMBA 3 AXI component of a SOC or a ASIC. The SmartDV's AMBA 3 AXI Verification IP is fully compliant with standard AMBA 3 AXI Specification and provides the following features.
AMBA 3 AXI VIP is supported natively in VMM, RVM, AVM, OVM, UVM, Verilog, SystemC and non-standard verification env
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Features
Compliant to AMBA 3 AXI Protocol
Supports AXI Arbiter, AXI Master, AXI Slave, AXI Interconnect, AXI MOnitor,
AXI Checker.
Support all AMBA 3 AXI Protocol data and address width
Support all AMBA 3 AXI Protocol transfer types and response
Support all AMBA 3 AXI Protocol burst transfers
Support for SASD, SAMD interconnect matrix
Multiple outstanding transactions
Out of order transactions
Data interleaving
AXI Interconnect can support multiple Masters & Slaves
Assertions and Checks for protocol violations
Logs and report for bus traffic
Also includes User-configurable commands
Call backs and call back variables to provide control over test case execution
On-the-fly protocol and data checking
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Benefits
Faster testbench development and more complete verification of AMBA 3 AXI designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
Simplifies results analysis.
Runs in every major simulation environment.
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AMBA 3 AXI Verification Env
SmartDV's AMBA 3 AXI Verification env contains following.
- Complete SystemVerilog source code of AMBA 3 AXI Arbiter, AXI Master, AXI Slave, AXI Monitor and AXI Checker.
- Complete regression suite containing all the AMBA 3 AXI testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
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