USB Synthesizable VIP provides a smart way to verify the USB component of a SOC or a ASIC in Emulator or FPGA platform. It provides backward compatibility support for earliers versions of USB specifications. The SmartDV's USB Synthesizable VIP is fully compliant with standard USB Specification 1.0 and 2.0.
USB Synthesizable VIP data transfer can be done at different speeds which intuitively involves high speed (480Mbits/sec), full speed (12Mbits/sec) or low speed (1.5Mbits/sec).
- Features
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- USB 2.0
- Compatible with USB 1.1, USB 2.0
- Supports Standard USB 2.0 interface, UTMI, UTMI+, ULPI and HSIC interfaces
- Supports Standard DP/DM bus interface
- Operates at high, full and low speed
- Support HOST and Device model
- Supports up to 127 devices
- Supports completely configurable bus enumeration
- Supports all descriptor types and device requests
- Supports Link Power Management (LPM)
- All USB 2.0 transfer types (Control, Isochronous, Interrupt, Bulk) are supported
- Supports both transaction level (Setup, In, Out, Ping) and packet level (Token, Data, Handshake, SOF) transmission/reception
- Auto detection of device connection and disconnection
- Supports SRP and HNP compliance checking
- Provides SOF generation support
- Programmable inter packet and end-to-end delays
- Supports all types of error injection and detection
- Errors include:
- Corrupt Sync byte
- Corrupt PID Byte
- Corrupt CRC-5 Byte
- Corrupt CRC-16 Byte
- Corrupt Endpoint Address Byte
- Corrupt Setup Payload Size
- Corrupt Setup Stage Data Payload
- Corrupt EOP byte
- Bit stuffing error
- Programmable timers for suspend, resume and reset signaling
- USB 2.0 OTG
- Combination of OTG device communication
- OTG device to Embedded Host
- Targeted Host to peripheral only B-device
- OTG device to OTG device
- Supported devices
- Dual A device
- Dual B device
- Embedded host
- SRP only B device
- Supported protocols
- SRP
- HNP
- HNP polling
- Suspend/Resume/Remote wakeup
- ADP
- Supported speeds
- Supported feature selector
- b_hnp_enable
- a_hnp_support
- a_alt_hnp_support
- Support the all timeout condition
- a_wait_vrise_tmout
- a_wait_vfall_tmout
- a_wait_bcon_tmout
- a_aidl_bdis_tmout
- a_bidl_adis_tmout
- Support for bus drop and over current condition
- USB 3.0
- Compliant with USB 3.0 specification version 1.0
- Compliant with USB 3.0 Super speed Inter chip supplement 1.0
- Supports All RRAP Packet types
- Supports LS and HS burst
- Supports all LS and HS gears
- Supports all protocol error detection
- Supports all MPHY protocol error injection
- Supports MPHY RMMI and serial interface
- Complete solution for through chip-level verification
- Supports Superspeed USB 3.0 and USB 2.0 OTG
- Supports UTMI and PIPE interfaces
- Comprehensive model supports a Host, Device, Hub, PHY
- Configurable PHY Interface width 8, 16 or 32 bits
- Supports dual-simplex, four-wire differential signaling and 8b/10b parallel interface
- PHY interface supports data scrambling to reduce EMI emissions
- USB 2.0 device and host with UTMI/ULPI interfaces
- Operates at Super speed (5 Gbit/s), High(480 Mbit/s) or Full speed(12 Mbit/s) modes
- Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
- Supports Interrupt /Bulk/Isochronous/Control Transfers
- Control transfers supported by Endpoint 0
- Supports Low frequency periodic signaling (LFPS) for initialization and power management (U1, U2 & U3)
- Separate Endpoint Buffers for IN bound and OUT bound packets
- USB 3.0 low power states support
- Supports Bulk Stream
- Supports all types of error injection and detection
- Supports error injection in all the layers of USB 3.0
- USB 3.0 OTG
- Supported devices:
- SS-OTG
- SSPC-OTG Devices
- SS-PO Devices
- SS-EH Devices
- Support for USB 2.0:
- SS-OTG or SSPC-OTG devices operate as USB 2.0 OTG devices
- SS-EH operate as USB 2.0 EH
- SS-PO operate as USB 2.0 PO devices
- Supported protocols:
- SRP
- HNP
- ADP
- RSP for USB 3.0
- Supported speeds:
- Supported feature selector:
- b_hnp_enable
- a_hnp_support
- a_alt_hnp_support
- NTF_HOST_REL
- B3_RSP_ENABLE
- Support the all timeout condition:
- a_wait_vfall_timout
- a_wait_vrise_timout
- a3_polling_tmout
- a3_recovery_tmout
- a3_rx_detect_active_tmout
- rsp_cnf_err_tmout
- rsp_ack_err_tmout
- rsp_wrst_err_timout
- b3_polling_tmout
- b3_recovery_tmout
- b3_rx_detect_active_tmout
- Combination of SSPC-OTG device communication:
- SSPC-OTG device to SSPC-OTG device
- SSPC-OTG device to SS-OTG device
- SS-OTG device to SSPC-OTG device
- SSPC-OTG device to USB 2.0 OTG
- USB 2.0 OTG device to SSPC-OTG device
- USB 3.1
- In addition to USB3.0 features USB3.1 supports the following features:
- Compliant with USB 3.1 specification version 1.0
- Supports dual-simplex, four-wire differential signaling and 128b/132b parallel interface
- Operates at SuperSpeedPlus (10 Gbit/s), Super speed (5 Gbit/s), High speed(480 Mbit/s) or Full speed(12 Mbit/s) modes
- Backward compatible with USB 3.0, USB 2.0 and USB 1.0
- USB 3.1 host and device with SERIAL/PIPE interfaces
- Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
- Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
- Supports SuperSpeedPlus Precision Time Measurement
- Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
- Rich set of configuration parameters to control the functionality
- On-the-fly protocol and data checking
- Benefits
-
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- USB Synthesizable VIP Env
-
SmartDV's USB Synthesizable VIP env contains following:
- Synthesizable transactors
- Complete regression suite containing all the USB testcases
- Examples showing how to connect various components, and usage of Synthesizable VIP
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
