UFS Synthesizable Transactor is compliant with JESD220B UFS specification and verifies UFS devices. UFS is build on top of it to make it robust. UFS Synthesizable Transactor provides a smart way to verify the UFS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's UFS Synthesizable Transactor is fully compliant with standard JESD220B UFS specification and provides the following features.
- Features
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- Full UFS Host and Device functionality
- Supports UFS 2.1 draft specification
- Supports high performance M-PHY type-1
- Supports full UFS Host and Device functionality
- Supports UFS driver layer over UniPro
- Supports VIP interface at MPHY Serial, MPHY RMMI, Unipro CPort level
- Supports UFS-Specified commands of Specification JESD220B
- Supports Unified Memory Extension JESD220-1(Version 1.0)
- Supports various UFS layers
- UFS Command Set Layer (UCS)
- UFS Transport Protocol Layer (UTP)
- UFS Interconnect Layer (UIC)
- Includes MIPI UniPro and M-PHY VIP for UFS Interconnect Layer verification
- MIPI UniPro is adopted for data link layer
- MIPI M-PHY is adopted for physical layer
- 1 and 2 lane support
- All PWM gears support
- All HS gears support
- All DME commands supported
- Enter hibernate and exit hibernate supported
- Complex LSS feature verification support to cover all cases, Like lane mapping, reverse lane mapping, errors in UPR sequences etc
- Various types of error injection at Unipro and MPHY layers
- L1.5 and Cport test mode features supported
- Advanced L1.5, L2 and Cport error injection
- All L2 Preemption and error cases supported
- Supports Unipro 1.41 and Unipro 1.6 specs
- Low power with multiple power operating modes
- Supports boot mode operation
- Supports device enumeration and discovery
- Supports Multiple partitions (LUNs) with partition Management
- Supports Multiple User Data Partition with Enhanced User Data Area options
- Supports boot partitions and RPMB partition
- Supports Reliable write operation
- Supports Background operations
- Supports Secure operations, Purge and Erase to enhance data security
- Supports Write Protection options, including Permanent & Power-On Write Protection
- Supports Signed access to a Replay Protected Memory Block
- Supports HW Reset Signals
- Supports Task management operations
- Supports Power management operations
- Supports automatic/user tag generation
- Supports Error injection and detection in all levels of UFS protocol
- Supports all types of error injection and detection
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- UFS Synthesizable Transactor Env
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SmartDV's UFS Verification env contains following:
- Synthesizable transactors
- Complete regression suite containing all the UFS testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
