DMX Synthesizable Transactor provides a smart way to verify the DMX component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DMX Synthesizable Verification IP is fully compliant with standard DMX Specification and provides the following features.
- Features
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- Fully compatible with American National Standard E1.11 - 2008 (R2013) Specification
- Supports transmit and receive commands that allow the user to transmit and receive DMX512 packets
- Supports fully configurable serial interface
- Supports programmable clock frequency of operation
- Supports configurable baud rate
- Supports the reset sequence
- Supports all reserved alternative start codes
- Supports up to maximum of 513 slots
- Supports ASCII Text character set encoding technique
- Supports UTF-8 Text character set encoding technique
- Supports all types of error insertion and detection
- Minimum break length error
- Maximum break length error
- Invalid start code error
- Maximum mark before break error
- Minimum mark after break error
- Maximum mark after break error
- Break to break timeout errors
- DMX512 packet timeout errors
- Start bit error
- Stop bit error
- 16-Bits checksum error
- 8-Bits checksum error
- Wrong SIP sequence number error
- Timeout errors
- Supports glitch insertion and detection
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- DMX Synthesizable Env
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SmartDV's DMX Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the DMX testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
