USB Verification IP provides an smart way to verify the USB 1.0/2.0/3.0/3.1 component of a SOC or a ASIC. It provides backward compatibility support for earliers versions of USB specifications. The SmartDV's USB Verification IP is fully compliant with standard USB Specification 1.0, 2.0, 3.0 and 3.1.
USB VIP data transfer can be done at different speeds. Which intuitively involves super speed plus (10 Gbit/s), super speed (5 Gbit/s), high speed(480 Mbit/s), full speed(12 Mbit/s) or low speed(1.5Mbit/s). The USB VIP includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively. This way it detects the violation of protocol completely.
USB VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Features
-
- USB 2.0
- Compatible with USB 1.1 and USB 2.0 specification
- Supports Standard USB 2.0 interface, UTMI, UTMI+, ULPI and HSIC interfaces.
- Standard DP/DM bus interface is supported.
- Operates at high, full and low speed.
- Support HOST and Device model.
- Supports up to 127 devices.
- Supports completely configurable bus enumeration.
- Supports all descriptor types and device requests.
- Supports Link Power Management (LPM).
- Supports constrained randomization of protocol attributes.
- All USB2.0 transfer types (Control, Isochronous, Interrupt, Bulk) are supported.
- Supports both transaction level (Setup, In, Out, Ping) and packet level (Token, Data, Handshake, SOF) transmission/reception.
- Constrained driven randomization of packets achieved by randomization of various fields of the packet.
- Auto detection of device connection and disconnection.
- Supports SRP and HNP compliance checking.
- Provides SOF generation support.
- Programmable inter packet and end-to-end delays.
- Proficiency to generate random packets/transactions and respond to packets/transactions in directed or randomized fashion.
- Supports all types of error injection and detection. Errors include:
- Corrupt Sync byte
- Corrupt PID Byte
- Corrupt CRC-5 Byte
- Corrupt CRC-16 Byte
- Corrupt Endpoint Address Byte
- Corrupt Setup Payload Size
- Corrupt Setup Stage Data Payload
- Corrupt EOP byte
- Bit stuffing error.
- Programmable timers for suspend, resume and reset signaling.
- USB 2.0 OTG
- Combination of OTG device communication
- OTG device to Embedded Host
- Targeted Host to peripheral only B-device
- OTG device to OTG device
- Supported devices
- Dual A device
- Dual B device
- Embedded host
- SRP only B device
- Supported protocols
- SRP
- HNP
- HNP polling
- Suspend/Resume/Remote wakeup
- ADP
- Supported speeds
- Supported feature selector
- b_hnp_enable
- a_hnp_support
- a_alt_hnp_support
- Support the all timeout condition
- a_wait_vrise_tmout
- a_wait_vfall_tmout
- a_wait_bcon_tmout
- a_aidl_bdis_tmout
- a_bidl_adis_tmout
- Support for bus drop and over current condition
- USB 3.0/3.1 Common support
- Compliant with USB 3.0/3.1 specification version 1.0
- Supports Superspeed USB 3.0, SuperSpeedPlus 3.1 and 3.0 OTG
- Complete solution for thorough chip-level verification
- Comprehensive model support a Host, Device, Hub, PHY
- Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
- Configurable PHY Interface width 8, 16 or 32 bits
- PHY interface supports data scrambling to reduce EMI emissions
- Comprehensive compliance testsuite for Protocol, Link, and Physical layer verification
- Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
- Supports Interrupt/Bulk/Isochronous/Control Transfers
- Control transfers supported by Endpoint 0
- Separate Endpoint Buffers for IN bound and OUT bound packets
- Supports for USB 3.0/3.1 low power states
- Bulk Stream support
- USB 3.0
- Compliant with USB 3.0 specification.
- Compliant with USB 3.0 Super speed Inter chip supplement 1.0.
- USB 3.0 host and device with SERIAL/PIPE/SSIC interfaces
- Supports SS-OTG,SSPC-OTG Devices,SS-PO Devices and SS-EH Devices
- Backward compatible with USB 2.0 and USB 1.0
- Supports ADP,HNP,SRP and RSP
- Supports Inter-Chip Supplement to the USB Revision 3.0 Specification (Super Speed Inter-Chip) using MIPI MPHY
- Supports MPHY Type-I operations
- Supports MPHY all PWM 1 gear of operation
- Supports MPHY all HS 1,2,3 gear of operation
- Supports 1,2,4 lanes
- Supports all types of error injection in MPHY
- Supports All RRAP Packet types
- Supports LS and HS burst
- Supports all LS and HS gears
- Supports all protocol error detection
- Supports all MPHY protocol error injection
- Supports MPHY RMMI and serial interface
- Supports UTMI and PIPE interfaces.
- Supports dual-simplex, four-wire differential signaling and 8b/10b parallel interface.
- USB 2.0 device and host with UTMI/ULPI interfaces.
- Operates at Super speed (5 Gbit/s), High(480 Mbit/s) or Full speed(12 Mbit/s) modes.
- Supports all types of error injection and detection.
- Supports error injection in all the layers of USB 3.0.
- Supports constrained randomization of protocol attributes.
- Rich set of configuration parameters to control the functionality
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in host and device for various events.
- USB Verification IP comes with complete testsuite to test every feature of USB specification.
- USB 3.0 OTG
- Supported devices.
- SS-OTG
- SSPC-OTG Devices
- SS-PO Devices
- SS-EH Devices
- Support for USB 2.0.
- SS-OTG or SSPC-OTG devices operate as USB 2.0 OTG devices.
- SS-EH operate as USB 2.0 EH.
- SS-PO operate as USB 2.0 PO devices.
- Supported protocols.
- SRP
- HNP
- ADP
- RSP for USB 3.0
- Supported speeds.
- Supported feature selector.
- b_hnp_enable
- a_hnp_support
- a_alt_hnp_support
- NTF_HOST_REL
- B3_RSP_ENABLE
- Support the all timeout condition.
- a_wait_vfall_timout
- a_wait_vrise_timout
- a3_polling_tmout
- a3_recovery_tmout
- a3_rx_detect_active_tmout
- rsp_cnf_err_tmout
- rsp_ack_err_tmout
- rsp_wrst_err_timout
- b3_polling_tmout
- b3_recovery_tmout
- b3_rx_detect_active_tmout
- Combination of SSPC-OTG device communication.
- SSPC-OTG device to SSPC-OTG device
- SSPC-OTG device to SS-OTG device
- SS-OTG device to SSPC-OTG device
- SSPC-OTG device to USB 2.0 OTG
- USB 2.0 OTG device to SSPC-OTG device
- USB 3.1
- In addition to USB3.0 features, USB3.1 supports the following features
- Compliant with USB 3.1 specification version 1.0.
- Supports dual-simplex, four-wire differential signaling and 128b/132b parallel interface.
- Operates at SuperSpeedPlus (10 Gbit/s), Super speed (5 Gbit/s), High speed(480 Mbit/s) or Full speed(12 Mbit/s) modes.
- Backward compatible with USB 3.0, USB 2.0 and USB 1.0.
- USB 3.1 host and device with SERIAL/PIPE interfaces.
- Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports.
- Supports SuperSpeedPlus LFPS Based PWM Message (LBPM).
- Supports SuperSpeedPlus Precision Time Measurement.
- Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet.
- Benefits
-
- Faster testbench development and more complete verification of USB designs.
- Easy to use command interface simplifies testbench control and configurationof device and host.
- Simplifies results analysis.
- Runs in every major simulation environment.
- USB Verification Env
-
SmartDV's USB Verification env contains following.
- Complete regression suite containing all the USB testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
