MIL-STD-1553 Synthesizable VIP provides a smart way to verify the MIL-STD-1553 component of a SOC or a ASIC in Emulator or FPGA platform. The MIL-STD-1553 Synthesizable VIP is compliant with MIL-STD-1553B specification and verifies MIL-STD-1553 interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.
- Features
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- Compliant with MIL-STD-1553B Standard
- Supports Remote terminal, Bus Controller
- Supports configurable length of word length, default 20 bits
- Supports configurable length of data bits, default 16
- Supports configurable message length per transfer
- Supports NRZ and Manchester encoding
- Supports single or multi bus control
- Supports following message formates
- Controller to terminal
- Terminal to controller
- Terminal to terminal
- Broadcast
- System control
- Supports glitch injection and detection
- Supports upto 31 remote terminals
- Supports all types of errors insertion/detection as given below:
- Sync error
- Parity error
- NRZ or Manchester encoding error
- Glitch injection
- Oversize message error
- Undersize message error
- Driving X onto bus
- Various illegal values errors
- Inter message gap error
- Terminal response time error
- Supports testcases from following standards
- MIL-HDBK-1553 Remote Terminal Validation Test Plan Notice 1
- MIL-HDBK-1553A Remote Terminal Validation Test Plan Section 100
- SAE AS-4111 Remote Terminal Validation Test Plan
- SAE AS-4112 Remote Terminal Production Test Plan
- SAE AS-4113 Bus Controller Validation Test Plan
- SAE AS-4114 Bus Controller Production Test Plan
- SAE AS-4116 Bus Monitor Test Plan
- Supports on-the-fly protocol and data checking
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- MIL-STD-1553 Synthesizable Env
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SmartDV's MIL-STD-1553 Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the MIL-STD-1553 testcases
- Examples showing how to connect various components, and usage of Synthesizable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
