SmartDV Services

SmartDV offers design and verification services in the area of ASIC and FPGA design, with emphasis on quality deliverables. Our offerings are designed to function with minimal customer involvement, and the process ensures flawless and timely delivery be it designs starting from specifications or point services. SmartDV offers industry standard Verification IP like I2C, ethernet, AMBA, OCP, PCIE, USB, SATA, LIN, Fiber Channel in Vera, and SystemVerilog.

We have experience in building smart verification env in HVL like E (specman), VERA, SystemC, TestBuilder (C++), NTB, and SystemVerilog. We have vast experience in usage of buliding verification env with RVM, VMM, AVM, eRM, OVM

Verification Services

• We have experience in writing Verification enviroment for very complex ASIC's (40+ Million gate design).
• We can develop verification enviroment in Vera, SystemVerilog, E and SystemC.
• We have experience in writing testbenches using RVM, VMM, AVM, eRM, OVM.
• We use lot of automation in writing testbenched so we can write testbenches very fast.
• We have big list of Verification IP's which we can plug into any verification env and get jump start on project.
• Code Coverage, Functional coverage and Assertion coverage driven verification.

SystemVerilog Migration

SmartDV provides migration services to speed the transition from legacy languages and environments to the widely supported IEEE 1800 SystemVerilog language. SmartDV SystemVerilog migration services enable companies to easily take advantage of legacy verification environments while adopting the widely supported industry standard SystemVerilog.

Services include translation of verification components from such as bus functional models, Assertions and random traffic generators; migration of existing test suites; and validation of migrated verification environments. These services take advantage of SmartDV's extensive verification know-how with a wide range of high-level verification languages and methodologies. We have converted Specman E to SystemVerilog, and also Vera to SystemVerilog