SmartDV offers a unique opportunity for ambitious ASIC engineers. As a ASIC design and verification expert you will have range of projects to work with. You will have opportunity to work with industry's best talent.

At SmartDV you will get to work on technologies which are very innovative and will have chance to contribute to this innovative technologies. If you think you know next big thing in verification, or you think you can solve next big issue in verification, then SmartDV is right place for you.

Verification Engineer

  • 2-7+ Years of experience in ASIC verification
  • Should have tapped out atleast 1 chips from specs to post silicon debug
  • Should have experience in creating testbenches from scratch
  • Should have very good understanding of coverage driven verification closure
  • Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman))
  • Very good experience in writing scripts in Perl or Python or TCL
  • Independent team player with excellent communication skills
  • Knowledge of C++
  • Preference is given for students from IIT and NIT's

Send resumes to jobs@smart-dv.com

Design Engineer

  • 2 to 7+ Years of experience in ASIC design
  • Expertise in micro-architecture, design of design blocks (IP) to system-on-chip (SoC) components
  • Experience in one/more of the following system bus interfaces like PCI Express, USB, SATA, SDIO, MIPI and /or AMBA.
  • Knowledge of SVA
  • Knowledge of memory controllers, CPU architecture is a plus
  • Knowledge of considerations for performance, power and cost optimization is desirable
  • Looking for highly motivated individuals and ability to deal with ambiguity
  • Ability to work in a team environment
  • Good debugging and problem solving skills
  • Ability to work with external technology companies for combined development of SOCs
  • Strong knowledge of Verilog
  • Very good experience in writing scripts in Perl or Python or TCL
  • Independent team player with excellent communication skills

Send resumes to jobs@smart-dv.com

Engineer Trainee

  • B.E or MTech from reputed university with 0-2 years experience.
  • Strong understanding of Digital design
  • Working experience with Verilog or VHDL or SystemVerilog
  • Experience in writing C or C++
  • Understanding of OOPS.
  • Knowledge of Perl or Python or TCL scripting languages
  • Very good academic track record

Send resumes to jobs@smart-dv.com



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