FEC RS (254,250) Decoder core is compliant with standard VESA DisplayPort version 1.4/2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (254,250) Decoder IIP is proven in FPGA environment. The host interface of the FEC RS (254,250) Decoder can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
FEC RS (254,250) Decoder IIP is supported natively in Verilog and VHDL
- Features
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- VESA Display Port version 1.4/2.0 compliant.
- Supports full FEC decoder functionality.
- Supports Reed Solomon (254,250) FEC, 10-bit symbols.
- Supports two-way interleaving for lane 1, lane 2 and lane 4 modes.
- Supports enable of FEC decoders based on lane mode.
- Supports RS decoder to correct errors up to two RS parity symbols.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's FEC RS (254,250) Decoder IP contains following
- The FEC RS (254,250) Decoder interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
