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RoCE Verification IP

RoCE Verification IP

RoCE Verification IP is compliant with InfiniBandTM Architecture Specification Volume 1 Release 1.2.1 for RDMA Over Converged Ethernet and IEEE 802.3 Specification. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment.

RoCE Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

RoCE Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports the RoCEv1 and RoCEv2
  • Supports the following Infini Band transport services
    • Reliable Connection
    • Reliable Datagram
    • Unreliable Connection
    • Unreliable Datagram
  • Supports the following upper layer protocols
    • IPV4
    • IPV6
    • UDP
  • Supports the following Transport functions
    • SEND
    • RESYNC
    • RDMA READ
    • RDMA WRITE
    • ATOMIC
  • Supports the following Transport Headers
    • Base Transport Header
    • Extended Transport Header
  • Supports priority flow control of Ethernet
  • Supports Ethernet 10G/25G/40G/50G/100G/200G and 400G Ethernet Speeds
  • Supports Glitch insertion and detection
  • Supports all types of TX and RX errors insertion/detection at each layer.
  • Comes with Tx BFM, Rx BFM, and Monitor
  • Supports Pause frame generation and detection
  • Callbacks in master and slave for various events
  • Status counters for various events in bus
  • Supports insertion of scrambler errors.
  • Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Supports constraints Randomization.
  • Supports bus accurate timing and timing checks.
  • RoCE Verification IP comes with complete test suite to test every feature of RoCE specification.
  • Functional coverage for complete RoCE features.
Benefits
  • Faster testbench development and more complete verification of RoCE designs
  • Easy to use command interface simplifies testbench control and configuration of TX and RX
  • Simplifies results analysis
  • Runs in every major simulation environment
RoCE Verification Env

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    SmartDV's RoCE Verification env contains following.

  • Complete regression suite (UNH) containing all the RoCE testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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