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TCAM Synthesizable Transactor

TCAM Synthesizable Transactor

TCAM Synthesizable Transactor provides a smart way to verify the TCAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's TCAM Synthesizable Transactor is fully compliant with standard TCAM Specification and provides the following features.

Features
  • Supports all the TCAM commands as per the specification
  • Supports 100% of TCAM protocol standard
  • Supports following commands,
    • Write
    • Read
    • Mask Write
    • Mask Read
    • Query
  • Supports flexible selection of width and depth
  • Supports flexible masking
  • Supports single-cycle write, read and search operation
  • Supports match-found and match-done flags to check the provided key availability during search operation
  • Checks for following,
    • Availability of key
    • Response time for the provided key
  • Quickly validates the implementation of the TCAM protocol
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
TCAM Synthesizable Transactor Env

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    SmartDV's TCAM Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the TCAM testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

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