• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

LPDDR5X Synthesizable Transactor

LPDDR5X Synthesizable Transactor

LPDDR5X Synthesizable Transactor provides a smart way to verify the LPDDR5X component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR5X Synthesizable Transactor is fully compliant with standard LPDDR5X Specification and provides the following features.

Features
  • Supports 100% of LPDDR5X protocol draft JEDEC specification and JESD209-5B specification.
  • Supports all the LPDDR5X commands as per the specs.
  • Supports device density up to 32GB.
  • Supports X8 and X16 device modes.
  • Supports 2:1 and 4:1 CKR mode.
  • Supports all data rates as per specification.
  • Supports system ECC function.
  • Supports burst length 16 and 32.
  • Supports programmable read/write latencies.
  • Supports BG, 8B and 16B bank organization modes.
  • Supports burst sequence.
  • Supports all mode register programming.
  • Supports write DBI and read DBI operation.
  • Supports write data mask operation.
  • Supports WCK2CK Sync operation.
  • Supports deep sleep mode.
  • Supports Optimized Refresh.
  • Supports Refresh Management Command.
  • Supports power down mode and self-refresh operation.
  • Supports frequency set point operation.
  • Supports following training modes
    • Command bus training
    • WCK2CK leveling
    • WCK-DQ training
    • Enhanced RDQS training mode
  • Supports partial array self refresh segment masking.
  • Supports write clock free running mode.
  • Supports data copy low power function and write x operation.
  • Supports hybrid refresh mode and refresh credit mode.
  • Supports CA parity and ECC.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Protocol checker fully compliant with LPDDR5X draft JEDEC specification and JESD209-5B specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
LPDDR5X Synthesizable Transactor Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's LPDDR5X Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the LPDDR5X testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.